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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC74VHC4053/D Advance Information Demultiplexer Analog Multiplexer/ MC74VHC4053 High-Performance Silicon-Gate CMOS The MC74VHC4053 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND). The VHC4053 is identical in pinout to the high-speed HC4053A, and the metal-gate MC14053B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. For a multiplexer/demultiplexer with channel-select latches, see VHC4351. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC - GND) = 2.0 to 6.0 V * Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V * Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts * Low Noise * In Compliance With the Requirements of JEDEC Standard No. 7A * Chip Complexity: VHC4053 -- 156 FETs or 39 Equivalent Gates D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 ORDERING INFORMATION MC74VHCXXXXD MC74VHCXXXXDT SOIC TSSOP FUNCTION TABLE - MC74VHC4053 Control Inputs Enable L L L L L L L L H C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 LOGIC DIAGRAM MC74VHC4053 Triple Single-Pole, Double-Position Plus Common Off X0 13 X1 Y0 1 Y1 Z0 3 Z1 CHANNEL-SELECT INPUTS A 10 B 9 C 6 ENABLE 11 5 2 12 X SWITCH 14 X X = Don't Care Y SWITCH 15 ANALOG INPUTS/OUTPUTS Y COMMON OUTPUTS/INPUTS Pinout: MC74VHC4053 (Top View) Z SWITCH 4 Z VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch 1 Y1 2 Y0 3 Z1 4 Z 5 Z0 6 Enable 7 NC 8 GND This document contains information on a new product. Specifications and information herein are subject to change without notice. 10/98 (c) Motorola, Inc. 1998 1 REV 0 MC74VHC4053 II I I I IIIIIIIIIIIIIIIIIIIIIII I I II I III II I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC VIS Vin I Parameter Value Unit V V V Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 500 450 Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, Storage Temperature Range mA PD SOIC Package TSSOP Package mW Tstg TL - 65 to + 150 _C Lead Temperature, 1 mm from Case for 10 SecondsIIIIII 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v III I I I I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I Symbol VCC VIS Vin Parameter Min 2.0 0.0 Max 6.0 Unit V V V Positive DC Supply Voltage Analog Input Voltage (Referenced to GND) VCC VCC 100 Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND VIO* TA mV Operating Temperature Range, All Package Types - 55 + 125 RECOMMENDED OPERATING CONDITIONS _C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V ns/V 0 0 100 20 * For voltage drops across switch greater than 100 mV (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. MOTOROLA 2 VHC Data - Advanced CMOS Logic DL203 -- Rev 2 MC74VHC4053 DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 0.1 85C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 125C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 Unit Ui V Symbol S bl VIH Parameter P Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Condition C di i Ron = Per Spec VIL Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Ron = Per Spec V Iin ICC Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Vin = VCC or GND, Channel Select, Enable and VIS = VCC or GND; VIO = 0 V A A 6.0 4 40 160 I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I I I II I I I II III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I I III I I I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I Guaranteed Limit Symbol S bl Ron Parameter P Test C di i T Conditions VCC V 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 6.0 - 55 to 25_C 25 18 15 20 15 10 DC ELECTRICAL CHARACTERISTICS Analog Section v 85_C v 125_C 30 23 20 25 20 15 35 28 25 30 25 20 25 15 10 Unit Ui Maximum "ON" Resistance Vin = VIL or VIH VIS = VCC to GND IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = VCC or GND (Endpoints) IS 2.0 mA (Figures 1, 2) v v Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Ioff Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel Maximum On-Channel Leakage Current, Channel-to-Channel Vin = VIL or VIH VIS = 1/2 (VCC - GND) IS 2.0 mA Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) v 15 8.0 4.0 20 12 7.0 0.1 0.5 1.0 A Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4) 6.0 0.1 1.0 2.0 Ion Vin = VIL or VIH; Switch-to-Switch = VCC or GND; (Figure 5) 6.0 0.1 1.0 2.0 A VHC Data - Advanced CMOS Logic DL203 -- Rev 2 3 MOTOROLA MC74VHC4053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns) Symbol S bl tPLH, tPHL Parameter P Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 30 20 15 15 4.0 3.0 1.0 1.0 30 20 15 15 20 12 8.0 8.0 10 35 50 1.0 85C 35 25 18 18 6.0 5.0 2.0 2.0 35 25 18 18 25 14 10 10 10 35 50 1.0 125C 40 30 22 20 8.0 6.0 2.0 2.0 40 30 22 20 30 15 12 12 10 35 50 1.0 pF Unit Ui ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) ns Cin CI/O Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I Feedthrough pF pF CPD Power Dissipation C P Di i i Capacitance (Fi i (Figure 13)* Typical @ 25C, VCC = 5.0 V 45 * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . MOTOROLA 4 VHC Data - Advanced CMOS Logic DL203 -- Rev 2 MC74VHC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V Limit* 25C Unit Ui MHz 3.0 30 4.50 6.00 3.0 4.50 6.00 3.0 4.50 6.00 3.0 4.50 6.00 3.0 4.50 6.00 3.0 4.50 6.00 3.0 4.50 6.00 120 120 120 -50 -50 -50 -40 -40 -40 25 105 135 35 145 190 -50 -50 -50 -60 -60 -60 % 3.0 4.50 6.00 0.10 0.08 0.05 dB mVPP dB Symbol S bl BW Parameter P Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 6) Condition C di i fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase fi Frequency Until dB Meter in Reads -3dB; RL = 50, CL = 10pF fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF -- Off-Channel Feedthrough Isolation (Figure 7) fin = 1.0MHz, RL = 50, CL = 10pF -- Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF RL = 10k, CL = 10pF -- Crosstalk Between Any Two Switches (Figure 12) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF fin = 1.0MHz, RL = 50, CL = 10pF THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured - THDsource VIS = 2.0VPP sine wave VIS = 4.0VPP sine wave VIS = 5.5VPP sine wave * Limits not tested. Determined by design and verified by qualification. Ron , ON RESISTANCE (OHMS) 200 125C 150 Ron , ON RESISTANCE (OHMS) 250 100 80 60 125C 25C TBD 100 25C TBD 40 20 - 55C - 55C 50 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 3.0 V VHC Data - Advanced CMOS Logic DL203 -- Rev 2 5 MOTOROLA MC74VHC4053 105 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 90 75 60 45 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 125C 25C 75 60 45 125C 25C TBD - 55C TBD 30 15 - 55C 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1c. Typical On Resistance, VCC = 4.5 V Figure 1d. Typical On Resistance, VCC = 6.0 V PLOTTER PROGRAMMABLE POWER SUPPLY - + MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND GND Figure 2. On Resistance Test Set-Up MOTOROLA 6 VHC Data - Advanced CMOS Logic DL203 -- Rev 2 MC74VHC4053 VCC VCC GND OFF VCC A NC OFF 16 VCC GND VCC 16 ANALOG I/O OFF OFF VCC COMMON O/I COMMON O/I VIH 6 8 VIH 6 8 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up VCC A ON GND VCC ANALOG I/O VIL 6 8 OFF 16 VCC fin COMMON O/I N/C 0.1F ON VCC 16 VOS dB METER CL* RL 6 8 *Includes all probe and jig capacitance Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up Figure 6. Maximum On Channel Bandwidth, Test Set-Up VIS 0.1F fin RL OFF VCC 16 VOS dB METER CL* RL RL ON/OFF ANALOG I/O OFF/ON RL VCC 16 COMMON O/I RL CL* TEST POINT 6 8 VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance VCC GND Vin 1 MHz tr = tf = 3 ns 6 8 11 VCC CHANNEL SELECT *Includes all probe and jig capacitance Figure 7. Off Channel Feedthrough Isolation, Test Set-Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up VHC Data - Advanced CMOS Logic DL203 -- Rev 2 7 MOTOROLA MC74VHC4053 VCC VCC CHANNEL SELECT tPLH ANALOG OUT 50% GND tPHL 6 50% 8 CHANNEL SELECT *Includes all probe and jig capacitance ON/OFF ANALOG I/O OFF/ON CL* VCC 16 COMMON O/I TEST POINT Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out VCC 16 VCC 50% GND tPLH ANALOG OUT 50% tPHL 6 8 ANALOG I/O ON CL* COMMON O/I TEST POINT ANALOG IN *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out tf ENABLE tPZL ANALOG OUT 50% tr 90% 50% 10% tPLZ VCC GND HIGH IMPEDANCE 10% tPZH tPHZ VOL VCC 1 2 1 2 POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O ON/OFF CL* ENABLE 1k TEST POINT ANALOG OUT 90% 50% VOH HIGH IMPEDANCE 6 8 Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out MOTOROLA 8 VHC Data - Advanced CMOS Logic DL203 -- Rev 2 MC74VHC4053 VCC VIS VCC RL fin 0.1F OFF RL 6 8 *Includes all probe and jig capacitance RL CL* RL CL* 6 8 11 VCC ON 16 VOS ANALOG I/O OFF/ON ON/OFF 16 COMMON O/I NC A CHANNEL SELECT Figure 12. Crosstalk Between Any Two Switches, Test Set-Up 0 VCC 16 ON RL CL* VOS TO DISTORTION METER dB - 10 - 20 - 30 - 40 - 50 - 60 6 8 *Includes all probe and jig capacitance - 70 - 80 - 90 - 100 Figure 13. Power Dissipation Capacitance, Test Set-Up VIS 0.1F fin FUNDAMENTAL FREQUENCY DEVICE SOURCE 1.0 2.0 FREQUENCY (kHz) 3.125 Figure 14a. Total Harmonic Distortion, Test Set-Up Figure 14b. Plot, Harmonic Distortion APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swing is determined by the supply voltages VCC. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In this example, the difference between VCC and GND is five volts. Therefore, using the configuration of Figure 15, a maximum analog signal of five volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts When voltage transients above VCC and/or below GND are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. VHC Data - Advanced CMOS Logic DL203 -- Rev 2 9 MOTOROLA MC74VHC4053 VCC +5V 0V Dx Dx VEE 6 8 11 10 9 TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS VCC Dx Dx VEE +5V +5V 0V 16 ANALOG SIGNAL ON ANALOG SIGNAL VCC 16 ON/OFF 8 Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5V +5V GND 16 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V * R R +5V GND +5V GND 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL +5V GND R LSTTL/NMOS CIRCUITRY 6 8 11 10 9 VHC1GT50 BUFFERS +5V LSTTL/NMOS CIRCUITRY 6 8 11 10 9 * 2K R 10K a. Using Pull-Up Resistors b. Using HCT Interface Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs 11 LEVEL SHIFTER 13 A X1 12 14 B 10 LEVEL SHIFTER 1 X0 X Y1 2 15 C 9 LEVEL SHIFTER 3 Y0 Y Z1 5 4 ENABLE 6 LEVEL SHIFTER Z0 Z Figure 18. Function Diagram, VHC4053 MOTOROLA 10 VHC Data - Advanced CMOS Logic DL203 -- Rev 2 MC74VHC4053 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J 9 -A - 16 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S 16X K REF DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O M 0.10 (0.004) 0.15 (0.006) T U S TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ M DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E VHC Data - Advanced CMOS Logic DL203 -- Rev 2 11 EE CC EE CC -W- MOTOROLA MC74VHC4053 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps MOTOROLA 12 MC74VHC4053/D VHC Data - Advanced CMOS Logic DL203 -- Rev 2 |
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